Current sensing for flash

ABSTRACT

Sense amplifiers and memory devices include a current source coupled to a bit line connection, a sensing transistor having a control gate coupled to the bit line connection, and a data latch coupled to a source/drain region of the sensing transistor. The sensing transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier and/or the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of the semiconductor manufacturing process utilized to form the sense amplifier

RELATED APPLICATION

This is a continuation application of U.S. application Ser. No.12/748,741, titled “CURRENT SENSING FOR FLASH,” filed Mar. 29, 2010(allowed), which is a divisional application of U.S. application Ser.No. 11/486,591, titled “CURRENT SENSING FOR FLASH,” filed Jul. 14, 2006,now U.S. Pat. No. 7,688,635, each of which is assigned to the assigneeof the present invention and the entire contents of which areincorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and inparticular the present invention relates to EEPROM and Flash memorydevices.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. There are several different types of memoryused in modern electronics, one common type is RAM (random-accessmemory). RAM is characteristically found in use as main memory in acomputer environment. RANI refers to read and write memory; that is, youcan both write data into RAM and read data from RAM. This is in contrastto ROM, which permits you only to read data. Most RAM is volatile, whichmeans that it requires a steady flow of electricity to maintain itscontents. As soon as the power is turned off, whatever data was in RAMis lost.

Computers almost always contain a small amount of read-only memory (ROM)that holds instructions for starting up the computer. Memory devicesthat do not lose the data content of their memory cells when power isremoved are generally referred to as non-volatile memories. An EEPROM(electrically erasable programmable read-only memory) is a special typenon-volatile ROM that can be erased by exposing it to an electricalcharge. EEPROM comprise a large number of memory cells havingelectrically isolated gates (floating gates). Data is stored in thefloating gate field effect transistor (FET) memory cells in the form ofcharge on the floating gates. The floating gate is typically made ofdoped polysilicon, or non-conductive charge trapping layer (a floatingnode), such as nitride, is disposed over the channel region and iselectrically isolated from the other cell elements by a dielectricmaterial, typically an oxide. Charge is transported to or removed fromthe floating gate or trapping layer by specialized programming and eraseoperations, respectively, altering the threshold voltage of the device.

Yet another type of non-volatile memory is a Flash memory. A typicalFlash memory comprises a memory array, which includes a large number offloating gate memory cells. The cells are usually grouped into sectionscalled “erase blocks.” Each of the cells within an erase block can beelectrically programmed by tunneling charges to its individual floatinggate/node. Unlike programming operations, however, erase operations inFlash memories typically erase the memory cells in bulk eraseoperations, wherein all floating gate/node memory cells in a selectederase block are erased in a single operation. It is noted that in recentnon-volatile memory devices multiple bits have been stored in a singlecell by utilizing multiple threshold levels (multi-level cells or MLC)or a non-conductive charge trapping layer with the storing of datatrapped in a charge near each of the sources/drains of the memory cellFET.

A NAND architecture array of a EEPROM or Flash also arranges its arrayof non-volatile memory cells in a matrix of rows and columns, as aconventional NOR array does, so that the gates of each non-volatilememory cell of the array are coupled by rows to word lines (WLs).However, unlike NOR, each memory cell is not directly coupled to asource line and a column bit line. Instead, the memory cells of thearray are arranged together in strings, typically of 8, 16, 32, or moreeach, where the memory cells in the string are coupled together inseries, source to drain, between a common source line and a column bitline. It is noted that other non-volatile memory array architecturesexist, including, but not limited to AND arrays, OR arrays, and virtualground arrays.

A problem in modern Flash memory devices is that, as device sizes andfeatures are further reduced with improved processing, the operatingcurrent through a memory cell selected for read in the array is reduced.This reduced cell current can allow for difficulty sensing the datavalue/stored threshold voltage of a selected memory cell during readingand/or verifying the memory cell's stored data value. In particular,sensing difficulties can occur during the reading or verifying of amarginal memory cell, during the sensing of a stored data value that isclose to the logical window threshold, or the sensing of the multiplediffering possible threshold values of stored data in MLC cells.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternative methods of reading and verifying Flash memory arrays.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a system containing anon-volatile memory device in accordance with an embodiment of thepresent invention.

FIG. 2 is a simplified block diagram of a NAND architecture Flash memoryarray in accordance with an embodiment of the present invention.

FIGS. 3A-3C show diagrams detailing current sensing and sense amplifiersin accordance with embodiments of the present invention.

FIG. 4 is a simplified block diagram of a memory module in accordancewith an embodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that logical, mechanical and electricalchanges may be made without departing from the spirit and scope of thepresent invention. The terms wafer or substrate used in the followingdescription include any base semiconductor structure. Both are to beunderstood as including silicon-on-sapphire (SOS) technology,silicon-on-insulator (SOI) technology, thin film transistor (TFT)technology, doped and undoped semiconductors, epitaxial layers of asilicon supported by a base semiconductor structure, as well as othersemiconductor structures well known to one skilled in the art.Furthermore, when reference is made to a wafer or substrate in thefollowing description, previous process steps may have been utilized toform regions/junctions in the base semiconductor structure, and termswafer or substrate include the underlying layers containing suchregions/junctions. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the claims.

Embodiments of the present invention include memory devices and arraysthat sense data in floating gate or floating node field effecttransistor memory cells using a current sensing data read/verify processand sense amplifier. The current sensing process senses memory cells ofa non-volatile memory array utilizing a current sensing process thatplaces a current source, such as a pull-up transistor, to source currenton to the bit line. The voltage level of the bit line is then set bycurrent differential on the coupled bit line between the current beingprovided by the current source and the current being sunk from the bitline through the selected memory cell to the source line, which isdependent on the threshold voltage of its programmed or erased state. Ifthe selected memory cell is erased, current flows through the memorycell to the source line and the bit line voltage falls. If the selectedmemory cell is programmed, little or no current flows through the cell,dependant on the programmed threshold voltage level of the cell andapplied read select voltage on the gate of the memory cell, and the bitline voltage rises and is sensed by the sense amplifier. This allows thesense amplifier to operate without having to precharge the bit line to aknown voltage level, as conventional non-volatile memory data sensingprocess and sense amplifier require. In one embodiment, the currentsource is turned off after a data value has been sensed to reduce powerconsumption. In another embodiment, a transistor is coupled serially inline with the bit line to form a cascade amplifier to boost sensitivity.In yet another embodiment, NAND architecture memory devices and arraysread the various cells of strings of non-volatile memory cells utilizinga current sensing sense amplifier.

It is noted, while embodiments of the present invention are described inrelation to NAND architecture non-volatile read and verify processes,that other memory array architectures, such as NOR architecture memoryarray and virtual ground memory array embodiments of the presentinvention, are also possible and will be apparent to those skilled inthe art with the benefit of the present invention. It is also noted thatembodiments of the present invention include all non-volatile memorycell devices and memories that use Vt to determine data values, such as,but not limited to, memory cells that trap charge in an electricallyisolated regions, charge trapping/floating node memory cells andferromagnetic memory cells, and thus are not limited to floating gatememory cell arrays or memory devices.

FIG. 1 details a simplified diagram of a system 128 incorporating anon-volatile memory device 100 of an embodiment of the present inventionconnected to a host 102, which is typically a processing device ormemory controller. The non-volatile memory 100, such as a Flash memorydevice, has a control interface 106 and an address/data interface 108that are each connected to the processing device 102 to allow memoryread and write accesses. It is noted that in alternative embodiments,the address/data interface 108 can be divided into separate interfaces.Internal to the non-volatile memory device a control statemachine/control circuit 110 directs the internal operation; managing thenon-volatile memory array 112 and updating RAM control registers anderase block management registers 114. The RAM control registers andtables 114 are utilized by the control state machine 110 duringoperation of the non-volatile memory 100. The non-volatile memory array112 contains a sequence of memory banks or segments 116, each bank 116is organized logically into a series of erase blocks (not shown). Memoryaccess addresses are received on the address/data interface 108 of thenon-volatile memory 100 and divided into a row and column addressportions. On a read access, the row address is latched by the interfaceI/O buffer 104 and decoded by row decode circuit 120, which selects andactivates a row page (not shown) of memory cells and the other memorycells in their associated strings across a selected memory bank. The bitvalues encoded in the output of the selected row of memory cells areconnected from a local bit line/string (not shown) to a bit line (notshown) and detected by sense amplifiers 122 associated with the memorybank. The sense amplifiers 122 also typically include a data cache andwrite data latch circuits (not shown). The column address of the accessis also latched by the interface I/O buffer 104 and decoded by thecolumn decode circuit 124. The output of the column decode circuitselects the desired column data from the sense amplifier outputs andconnected to the data buffer 126 for transfer from the memory devicethrough the address/data interface 108. It is noted that in oneembodiment of the present invention, the column decode 124 may beoptionally placed between the memory array 112 and the sense amplifiers122. On a write access the row decode circuit 120 selects the row pageand column decode circuit selects write sense amplifiers 122. Datavalues to be written are connected from the data buffer 126 to the datacache and then to the write data latches of the write sense amplifiers122 selected by the column decode circuit 124 and written to theselected non-volatile memory cells (not shown) of the memory array 112.The written cells are then reselected by the row and column decodecircuits 120, 124 and sense amplifiers 122 so that they can be read toverify that the correct values have been programmed into the selectedmemory cells.

As stated above, two common types of non-volatile or Flash memory arrayarchitectures are the “NAND” and “NOR” architectures, so called for theresemblance which the basic memory cell configuration of eacharchitecture has to a basic NAND or NOR gate circuit, respectively. Inthe NAND array architecture, the memory cells of the memory array arearranged in a matrix similar to conventional RAM or ROM, such that thegates of each memory cell of the array are coupled by rows to word lines(WL). However each memory cell is not directly coupled to a source line(SL) and a column bit line (BL), as would be the case in the NORarchitecture style (a row and column matrix memory cells, each memorycell coupled between a source line and a bit line). Instead, in NAND,the memory cells of the array are arranged together in strings,typically of 8, 16, 32, or more each, where the memory cells in thestring are coupled together in series, source to drain, between a commonsource line and a column bit line. This allows a NAND array architectureto have a higher memory cell density than a comparable NOR array, butwith the cost of a generally slower access rate and programmingcomplexity.

FIG. 2 shows a schematic of a simplified NAND architecture floating nodeor trapping layer memory array 200 of a NAND Flash memory device of anembodiment of the present invention. It is noted that the memory array200 of FIG. 2 is for illustrative purposes and should not be taken aslimiting and that other NAND memory array embodiments of the presentinvention are possible and will be apparent to those skilled in the artwith the benefit of the present disclosure. In FIG. 2, a series of NANDmemory strings 220 are arranged in an array 200 and coupled to bit lines212 and source lines 214. In each NAND memory string 220, a series offloating gate or floating node memory cells 202 of embodiments of thepresent invention are coupled together source to drain to form the NANDstring 220 (typically having 8, 16, 32, or more cells). As describedabove, each floating gate/node memory cell FET 202 has a gate-insulatorstack formed over the channel region. To further enable operation, inone embodiment of the present invention, one or more NAND architecturememory strings 220 of the memory are shown formed in an isolationtrench, allowing the substrate of each isolation trench to beindividually biased for programming and erasure. The word lines 206couple across the NAND strings 220, coupling the control gates ofadjacent memory cells 202 enabling a single memory cell 202 in eachmemory string 220 to be selected. In each NAND memory string 220,impurity (N+ typically) doped regions are formed between each gateinsulator stack to form the source and drain regions of the adjacentmemory cells 202, which additionally operate as connectors to couple thecells of the NAND string 220 together. In one embodiment of the presentinvention, the N+ doped regions are omitted and a single channel regionis formed under the NAND memory string 220, coupling the individualmemory cells 202. Each NAND memory string 220 is coupled to select gates204 that are formed at either end of each NAND string 220 andselectively couple opposite ends of each NAND string 220 to a bit line212 and a source line 214. The select gates 204 are each coupled to gateselect lines, select gate drain {SG(D)} 210 and select gate source{SG(S)} 208, that control the coupling of the NAND strings to the bitlines 212 and source lines 214, respectively, through the select gates204. In FIG. 2, the substrate connection 222 is shown coupled to each.NAND string 220, allowing the memory cells 202 of each NAND string 220to be biased from the substrate.

A NAND architecture floating gate or floating node memory array isaccessed by a row decoder activating a row of memory cells by selectingthe word select line coupled to their gates. In addition, the word linescoupled to the gates of the unselected memory cells of each string arealso driven. However, the unselected memory cells of each string aretypically driven by a higher gate voltage so as to operate them as passtransistors and allowing them to pass current in a manner that isunrestricted by their stored data values. Current then flows from thesource line to the column bit line through each floating gate/nodememory cell of the series coupled string, restricted only by the memorycells of each string that are selected to be read. This places thecurrent encoded stored data values of the row of selected memory cellson the column bit lines. A column page of bit lines is selected andsensed, and then individual data words are selected from the sensed datawords from the column page and communicated from the memory device.

Common programming technique for Flash/EEPROM memories programs a bit orrow (commonly referred to as a page) of the memory by applying aprogramming voltage or series of programming voltage pulses to thecontrol gates of the selected memory cells and then programming orinhibiting the selected memory cells to either programmed thresholdlevel (typically to set at logical “0” by the injection of charge to thefloating gate or floating node of a memory cell) or inhibited level (thecell is not programmed and left in its original state, usually intendedto leave the cell erased and set at logical “1”) by coupling thechannels of the memory cells to either a program or inhibit voltage. Itis noted that some erase operations also include program cycles. Theseerasure program cycles are typically used to preprogram the cells to auniform programmed threshold voltage before erasure and to “heal”over-erased memory cells to a uniform erased state threshold voltageafterwards. It is noted that the above described programming operationis for illustrative purposes and should not be taken as limiting.

After programming the selected memory cell(s), a verify operation isthen performed to confirm that the data was successfully programmed. Ifthe programmed memory cell(s) fail verification, the program and verifycycle is repeated until the data is successfully programmed or aselected number of iterations have passed and the programming operationis deemed to have failed.

As stated above, common data value reading/sensing technique forFlash/EEPROM memories selects and activates a row page (not shown) ofmemory cells (and the other memory cells in their associated strings ifa NAND architecture array by the application of a read pass voltageapplied to the unselected memory cell control gates of the strings)across a selected memory bank of the array by applying a read voltage totheir associated control gates. The bit values encoded in programmed orerased threshold voltage levels (typically, for a single level cell, setat logical “0” if programmed by the injection of charge to the floatinggate or floating node of a memory cell, raising the threshold voltage ofthe cell required to make the cell conducting, or, if unprogrammed, lefterased and set at logical “1”) of the memory cells of the selected roware output by being coupled from a local bit line/string (not shown) toa bit line (not shown) and detected by the sense amplifiers.

Prior art Flash/EEPROM memories the sense amplifiers sense the bitvalues placed on the bit lines by first pre-charging a voltage on thebit lines before they are coupled to the selected memory cells. The eachselected memory cell after it is coupled to the bit line either altersthe pre-charged bit line voltage (if it allows current flow to itscoupled source line, in other words, is unprogrammed) or does not alterthe pre-charged bit line voltage (if it is programmed and its thresholdvoltage is such that it does not turn on when the control gate readvoltage is applied). Multi-level memory cells (MLC's) are readsimilarly, although differing control gate read voltages are utilized todifferentiate between the differing possible programmed thresholdvoltage states. As such, when a memory cell's programmed state ismarginal, the memory cell has been program or read disturbed, or noiselevels in the voltage supply are high, errors or mis-reads of theprogrammed data values can occur. In particular, with MLC cells withtheir closely spaced logic threshold windows. In addition, withdecreasing feature sizes, operating voltage levels, and memory cellarray pitch, of modern non-volatile memory devices and arrays theseissues are increasing in significance due to smaller current flowsthrough memory cells, larger arrays, longer bit lines, smaller thresholdvoltage logic windows, and increased potential for memory cell disturbevents.

As stated above, embodiments of the present invention includenon-volatile memory devices and arrays that sense the programmedthreshold voltage levels/data of various cells of non-volatile memorycells utilizing a current sensing data read/verify process and senseamplifier. The current sensing process senses memory cells of anon-volatile memory array utilizing a current sensing process thatplaces a current source, such as a pull-up transistor, to source currenton to the bit line. The voltage level of the bit line is then set bycurrent differential on the coupled bit line between the limited currentbeing provided by the current source and the current being sunk from thebit line through the selected memory cell to the source line, which isdependent on the threshold voltage of its programmed or erased state. Ifthe selected memory cell is erased, current flows through the memorycell to the source line and the bit line voltage falls and is sensed bythe sense amplifier. If the selected memory cell is programmed, littleor no current flows through the cell, dependant on the programmedthreshold voltage level of the cell and applied read select voltage onthe gate of the memory cell, and the bit line voltage rises and issensed by the sense amplifier. This allows the sense amplifier tooperate without having to precharge the bit line to a known voltagelevel, as conventional non-volatile memory data sensing process andsense amplifier require. Elimination the need to precharge the bit linespeeds the read/sensing process and saves power.

FIGS. 3A, 3B and 3C illustrate a typical NAND architecture memory arrayand string programming operations of an embodiment of the presentinvention utilizing a current sensing data read/verify process to sensethe programmed threshold voltage levels/data of various cells ofnon-volatile memory cells. It is noted that the NAND read/sensingoperations described in FIGS. 3A, 3B and 3C are for illustrativepurposes and should not be taken as limiting. It is also noted thatwhile embodiments of the present invention in FIGS. 3A, 3B and 3C aredescribed in relation to NAND architecture non-volatile read and verifyprocesses, that other memory array architectures, such as NORarchitecture memory array and virtual ground memory array embodiments ofthe present invention, are also possible and will be apparent to thoseskilled in the art with the benefit of the present invention.

FIG. 3A illustrates an embodiment of a memory 300 of the presentinvention showing a memory cell of the array being read/sensed. In FIG.3A, a non-volatile memory cell 302 that has been selected to beread/sensed has a read voltage coupled to its control gate 304 and iscoupled to a bit line 306 and a source line 324. The bit lines 306 ofthe array are coupled to a column multiplexer 308 which selects the bitline 306 and memory cell 302 that is to be coupled to the senseamplifier 310 to be read. The sense amplifier 310 incorporates a currentsource 312, in the form of a regulated pull-up transistor that iscoupled to the selected bit line 306 and provides/sources current on tothe bit line 306. If the selected memory cell 302 is erased, it will befully or partially turned on by the selected read voltage applied to itsword line/control gate 304 and current will flow from the coupled bitline 306 through the selected memory cell 302 to the source line 324,which is coupled to ground or another appropriate low voltage potential.This drain of current from the bit line 306 through the erased memorycell 302 will over come the current being provided to the bit line 306from the current source 312 and lower the voltage potential on the bitline 306. If the memory cell 302 selected to be read is programmed, orotherwise has a threshold voltage high enough that the selected memorycell 302 is not turned on or is only marginally turned on by theselected read voltage applied to its word line/control gate 304, currentwill not flow from the coupled bit line 306 through the selected memorycell 302 to the source line 324. This allows the current source 312 toraise voltage potential of the bit line.

The raised or lowered voltage potential of the bit line is then sensedby a sensing transistor 318 that has its control gate coupled to the bitline 306. The sensing transistor 318 is coupled to a data latch 320,formed in the sense amplifier 310 by two feedback coupled inverters. Thedata latch 320 is typically reset to output a known state, such aslogical “0” or ground on its output 322 before the memory senses aselected memory cell 302. The sensing transistor 318 is preferably along channel transistor to allow for greater output variation andsensitivity to changes in bit line voltage. The sensing transistor 318in FIG. 3A is a long channel NFET transistor that, if the bit linevoltage is high (the selected memory cell 302 is programmed), sets thedata latch 320 by coupling the input side of the data latch 320 toground so that it expresses a high voltage/logical “1” on the output 322of the sense amplifier 310. If the bit line voltage is low, the sensingtransistor 318 does not turn on and leaves the data latch 320 in a resetstate, outputting a low voltage/logical “0” on the output 322. It isnoted that other sensing transistor 318/data latch 320 circuits arepossible, such as a PFET transistor coupled to Vcc and a latch formedfrom cross coupled NAND gates, and will be apparent to those skilled inthe art with the benefit of the present disclosure.

As stated above, the current source 312 in the embodiment of FIG. 3A isa regulated PFET pull-up transistor 312 that sources current from theupper power rail/Vcc 314 and has its current sourcing ability regulatedby a control voltage, Vcurr, applied to its control gate 316 so that itsources a known current on to the bit line 306. It is noted that, with aPFET transistor 312, as the voltage of the bit line 306 is brought belowthe voltage level of the control voltage, Vcurr, applied to its controlgate, the PFET transistor 312 cuts off and stops flowing current,allowing the bit line 306 voltage potential to be lowered in a quicklyby the current flowing through the coupled memory cell 302 and reducingoverall power consumption of the sensing circuit. It is also noted thatother current sources are possible, including, but not limited to NFETtransistors, current mirrors, diode coupled transistors, and pull-upresistors and will be apparent to those skilled in the art with thebenefit of the present disclosure. It is further noted that in oneembodiment, the current flows are reversed such that the current source316 is sinking current from the bit line 306.

Current sensing embodiments of the present invention allow for theprecharge stage of the read/sensing cycle to be reduced or eliminated,allowing for faster read cycles. In addition, current sensing is moreimmune to noise and power supply spikes and also allows for decreasedsensitivity to disturb conditions and closely spaced threshold voltagelevels/logic windows.

FIG. 3B illustrates another embodiment of a memory 330 of the presentinvention that cuts off current flow from the current source 312 after asuccessful read of the memory cell 302 in order to reduce powerconsumption. In FIG. 3B, a non-volatile memory cell 302 that has beenselected to be read/sensed has a read voltage coupled to its controlgate 304 and is coupled to a bit line 306 and a source line 324. Theselected bit line 306 of the array is coupled to the sense amplifier 310to be read through the column multiplexer 308. The sense amplifier 310incorporates a current source 312, in the form of a regulated pull-uptransistor that is coupled to the selected bit line 306 andprovides/sources current on to the bit line 306. If the selected memorycell 302 is erased, it will be turned on by the selected read voltageapplied to its word line/control gate 304 and current will flow from thecoupled bit line 306 through the selected memory cell 302 to the sourceline 324. If the memory cell 302 selected to be read is programmed, orotherwise has a threshold voltage high enough that the selected memorycell 302 is not turned on or is only marginally turned on by theselected read voltage applied to its word line/control gate 304, currentwill not flow from the coupled bit line 306 through the selected memorycell 302 to the source line 324. This allows the current source 312 toraise voltage potential of the bit line. The raised or lowered voltagepotential of the bit line is then sensed by a sensing transistor 318that has its control gate coupled to the bit line 306 and the valuecoupled to the data latch 320 and the output 322 of the sense amplifier310. In addition, in sense amplifier 310 of FIG. 3B, a current isolationtransistor 334 is placed between the incoming bit line 306 and thecurrent source 312. The current isolation transistor 334 has its controlgate coupled 332 to the output 322 of the sense amplifier 310 such that,once a logical “1” data value is latched in to the data latch 320 (i.e.,the current source 312 has raised the voltage potential of the bit line306 after having been coupled to a programmed memory cell 302), thecurrent source 312 is isolated from the coupled bit line 306 by theisolation transistor 334, preventing further current flow and reducingpower usage.

FIG. 3C illustrates yet another embodiment of a memory 340 of thepresent invention that utilizes a cascade amplifier. In FIG. 3C, anon-volatile memory cell 302 that has been selected to be read/sensedhas a read voltage coupled to its control gate 304 and is coupled to abit line 306 and a source line 324. The selected bit line 306 of thearray is coupled to the sense amplifier 310 to be read through thecolumn multiplexer 308. The sense amplifier 310 incorporates a currentsource 312, in the form of a regulated pull-up transistor that iscoupled to the selected bit line 306 and provides/sources current on tothe bit line 306. If the selected memory cell 302 is erased, it will beturned on by the selected read voltage applied to its word line/controlgate 304 and current will flow from the coupled bit line 306 through theselected memory cell 302 to the source line 324. If the memory cell 302selected to be read is programmed, or otherwise has a threshold voltagehigh enough that the selected memory cell 302 is not turned on or isonly marginally turned on by the selected read voltage applied to itsword line/control gate 304, current will not flow from the coupled bitline 306 through the selected memory cell 302 to the source line 324.This allows the current source 312 to raise voltage potential of the bitline. The raised or lowered voltage potential of the bit line is thensensed by a sensing transistor 318 that has its control gate coupled tothe bit line 306 and the value coupled to the data latch 320 and theoutput 322 of the sense amplifier 310.

In addition, in sense amplifier 310 of FIG. 3C, similar to FIG. 3B, atransistor 342 is placed between the incoming bit line 306 and thecurrent source 312. However, transistor 342 has its control gate coupledto a control voltage, V1, 344 instead of the output 322 of the senseamplifier 310. This allows the transistor 342 to operate as a cascadeamplifier in conjunction with the sensing transistor 318, such that, ifthe memory cell is programmed (no current flow) and V1 is less than thevoltage at the source of transistor 342 (the voltage at the sensingtransistor 318/current source 312), transistor 342 cuts off. Thisisolates the bit line from the sense amplifier 310 and allowing for afaster pull-up of the voltage potential at the sensing transistor 318 bythe current source 312. It is noted that transistor 342, like thesensing transistor 318, is preferably also a long channel transistor. Itis further noted that transistor 342 can also be a transistor that isutilized in the multiplexer 308 and serves a dual purpose in formingpart of the cascade amplifier.

In one embodiment of the present invention, a long channel transistor (aFET transistor that has a longer channel than the common channel lengthsand feature sizes of the semiconductor manufacturing process beingutilized and therefore has a more linear transfer function and thus amore resistive nature and a lower saturation current for a given controlgate voltage) or a current source with a higher internal resistance isutilized as the current source 312 of FIGS. 3A-3C to allow highersensitivity to current flow through the selected non-volatile memorycell by having a lower saturation current. In yet another embodiment,the sensing transistor 318 of FIGS. 3A-3C is a long channel transistorto allow for greater sensitivity to bit line voltage through a having ahigher resistive nature. In a further embodiment, the word line voltagelevel (Vwl) and current source control voltage (Vcurr) are set tospecific levels based on the threshold voltage group to be sensed in thememory cells. In yet a further embodiment, the word line voltage level(Vwl) is held at a selected level and the current source control voltage(Vcurr) is varied to sense for differing cell currents/threshold voltagelevels.

In yet another embodiment of the present invention, the current sensingallows for improved threshold voltage (Vt) redistribution formulti-level cell Flash memory by allowing for negative voltage Vt's tobe easily utilized and sensed. This makes the highest Vt of theprogrammed/erased cell smaller, improving data retention and reducingprogram voltages and the potential for memory cell disturb.

It is noted that the read/sensing operations and voltage levels of FIGS.3A-3C are for illustrative purposes and should not be taken as limiting.

FIG. 4 is an illustration of an exemplary memory module 400. Memorymodule 400 is illustrated as a memory card, although the conceptsdiscussed with reference to memory module 400 are applicable to othertypes of removable or portable memory, e.g., USB flash drives, and areintended to be within the scope of “memory module” as used herein. Inaddition, although one example form factor is depicted in FIG. 4, theseconcepts are applicable to other form factors as well.

In some embodiments, memory module 400 will include a housing 405 (asdepicted) to enclose one or more memory devices 410, though such ahousing is not essential to all devices or device applications. At leastone memory device 410 is a non-volatile memory including circuits of oradapted to perform elements of methods of the present invention. Wherepresent, the housing 405 includes one or more contacts 415 forcommunication with a host device. Examples of host devices includedigital cameras, digital recording and playback devices, PDAs, personalcomputers, memory card readers, interface hubs and the like. For someembodiments, the contacts 415 are in the form of a standardizedinterface. For example, with a USB flash drive, the contacts 415 mightbe in the form of a USB Type-A male connector. For some embodiments, thecontacts 415 are in the form of a semi-proprietary interface, such asmight be found on CompactFlash™ memory cards licensed by SanDiskCorporation, Memory Stick™ memory cards licensed by Sony Corporation, SDSecure Digital™ memory cards licensed by Toshiba Corporation and thelike. In general, however, contacts 415 provide an interface for passingcontrol, address and/or data signals between the memory module 400 and ahost having compatible receptors for the contacts 415.

The memory module 400 may optionally include additional circuitry 420which may be one or more integrated circuits and/or discrete components.For some embodiments, the additional circuitry 420 may include a memorycontroller for controlling access across multiple memory devices 410and/or for providing a translation layer between an external host and amemory device 410. For example, there may not be a one-to-onecorrespondence between the number of contacts 415 and a number of I/Oconnections to the one or more memory devices 410. Thus, a memorycontroller could selectively couple an I/O connection (not shown in FIG.4) of a memory device 410 to receive the appropriate signal at theappropriate I/O connection at the appropriate time or to provide theappropriate signal at the appropriate contact 415 at the appropriatetime. Similarly, the communication protocol between a host and thememory module 400 may be different than what is required for access of amemory device 410. A memory controller could then translate the commandsequences received from a host into the appropriate command sequences toachieve the desired access to the memory device 410. Such translationmay further include changes in signal voltage levels in addition tocommand sequences.

The additional circuitry 420 may further include functionality unrelatedto control of a memory device 410 such as logic functions as might beperformed by an ASIC (application specific integrated circuit). Also,the additional circuitry 420 may include circuitry to restrict read orwrite access to the memory module 400, such as password protection,biometrics or the like. The additional circuitry 420 may includecircuitry to indicate a status of the memory module 400. For example,the additional circuitry 420 may include functionality to determinewhether power is being supplied to the memory module 400 and whether thememory module 400 is currently being accessed, and to display anindication of its status, such as a solid light while powered and aflashing light while being accessed. The additional circuitry 420 mayfurther include passive devices, such as decoupling capacitors to helpregulate power requirements within the memory module 400.

It is noted that other current sensing read/verify operations, senseamplifiers, non-volatile memory array architectures, and voltage levelsfor non-volatile memory device and array embodiments of the presentinvention are possible and will be apparent for those skilled in the artwith the benefit of this disclosure.

CONCLUSION

A current sensing data read/verify process and sense amplifier isdescribed that senses memory cells of a non-volatile memory arrayutilizing a current sensing process that places a current source, suchas a pull-up transistor, to source current on to the bit line. Thevoltage level of the bit line is then set by current differential on thecoupled bit line between current provided by the current source in thesense amplifier and the current sunk from the bit line through theselected memory cell to the source line, which is dependent on thethreshold voltage of its programmed or erased state. If the selectedmemory cell is erased, current flows through the memory cell to thesource line and the bit line voltage falls and is sensed by the senseamplifier. If the selected memory cell is programmed, little or nocurrent flows through the cell, dependant on the programmed thresholdvoltage level of the cell and applied read select voltage on the gate ofthe memory cell, and the bit line voltage rises and is sensed by thesense amplifier. This allows the sense amplifier to operate withouthaving to precharge the bit line, as a conventional sense amplifierwould. In one embodiment, the sense amplifier current source is turnedoff after a data value has been sensed to reduce power consumption. Inanother embodiment, a transistor is coupled serially in line with thebit line to form a cascade amplifier.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

What is claimed is:
 1. A sense amplifier comprising: a current sourcecoupled to a bit line connection; a sensing transistor having a controlgate coupled to the bit line connection; and a data latch coupled to asource/drain region of the sensing transistor; wherein the sensingtransistor has a channel length greater than one and a half times thechannel length of a conventional transistor of a semiconductormanufacturing process utilized to form the sense amplifier.
 2. The senseamplifier of claim 1, further comprising an isolation transistor coupledbetween the current source and the bit line connection.
 3. The senseamplifier of claim 2, wherein the isolation transistor is coupled tooperate as a cascade amplifier in conjunction with the sensingtransistor.
 4. The sense amplifier of claim 2, wherein a control gate ofthe isolation transistor is coupled to an output of the sense amplifier.5. The sense amplifier of claim 2, wherein the isolation transistor hasa channel length greater than one and a half times the channel length ofa conventional transistor of the semiconductor manufacturing processutilized to form the sense amplifier.
 6. The sense amplifier of claim 2,wherein the isolation transistor comprises a transistor of a multiplexerthrough which the sense amplifier is coupled to a bit line.
 7. The senseamplifier of claim 1, wherein the sensing transistor comprises an NFETtransistor and another source/drain region of the sensing transistor iscoupled to a reference node.
 8. The sense amplifier of claim 7, whereinthe reference node comprises a ground.
 9. The sense amplifier of claim7, wherein the current source is adapted to source a selected current tothe bit line connection.
 10. The sense amplifier of claim 1, wherein thesensing transistor comprises a PFET transistor and another source/drainregion of the sensing transistor is coupled to a voltage supply node.11. The sense amplifier of claim 10, wherein the current source isadapted to sink a selected current from the bit line connection.
 12. Thesense amplifier of claim 1, wherein the current source comprises atransistor having a channel length greater than one and a half times thechannel length of a conventional transistor of a semiconductormanufacturing process utilized to form the sense amplifier.
 13. A memorydevice, comprising: a plurality of memory cells selectively coupled to abit line; and a sense amplifier selectively coupled to the bit line, thesense amplifier comprising: a current source coupled to a bit lineconnection selectively coupled to the bit line; a sensing transistorhaving a control gate coupled to the bit line connection; and a datalatch coupled to a source/drain region of the sensing transistor;wherein the sensing transistor has a channel length greater than one anda half times the channel length of a conventional transistor of asemiconductor manufacturing process utilized to form the senseamplifier.
 14. A sense amplifier comprising: a current source coupled toa bit line connection; a sensing transistor having a control gatecoupled to the bit line connection; a data latch coupled to asource/drain region of the sensing transistor; wherein the currentsource comprises a transistor having a channel length greater than oneand a half times the channel length of a conventional transistor of asemiconductor manufacturing process utilized to form the senseamplifier.
 15. The sense amplifier of claim 14, wherein the currentsource is adapted to either sink a selected current from the bit lineconnection or to source a selected current to the bit line connection.16. The sense amplifier of claim 14, wherein the sensing transistorcomprises an NFET transistor, another source/drain region of the sensingtransistor is coupled to a reference node, and the current source isadapted to source a selected current to the bit line connection.
 17. Thesense amplifier of claim 14, further comprising an isolation transistorcoupled between the current source and the bit line connection.
 18. Thesense amplifier of claim 17, wherein the isolation transistor comprisesa control gate, wherein the isolation transistor further comprises asource/drain region coupled to the current source, and wherein thecontrol gate of the isolation transistor is coupled to receive a voltagethat is less than a voltage the current source can develop on thesource/drain region of the isolation transistor.
 19. The sense amplifierof claim 17, wherein a control gate of the isolation transistor iscoupled to an output of the sense amplifier.
 20. A memory device,comprising: a plurality of memory cells selectively coupled to a bitline; and a sense amplifier selectively coupled to the bit line, thesense amplifier comprising: a current source coupled to a bit lineconnection; a sensing transistor having a control gate coupled to thebit line connection; a data latch coupled to a source/drain region ofthe sensing transistor; wherein the current source comprises atransistor having a channel length greater than one and a half times thechannel length of a conventional transistor of a semiconductormanufacturing process utilized to form the sense amplifier.